By Alford C.
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Extra info for Digital design VHDL laboratory notes
In the cshift component of logic_parts_pkg, input bit RL was used to indicate shift direction: RL=’0’ for left circular shift and ‘1’ for right circular shift. psd - View: PINS and REGS Printout produced: Thu Jun 13 01:46:57 1996 b b a a a a a a a a i i i i i i o o o o n n n n n n u u u u _ _ _ _ _ _ t t t t 0 1 0 1 2 3 _ _ _ _ | | | | | | 0 1 2 3 | | | | | | | | | | ^^^^^^^^^^^^^^^^^^^^^^^^^^^ 0: 0 1 0 0 1 0 L L L L 1: 0 1 0 0 1 0 L L L L 2: 0 1 0 0 1 0 L L L L 3: 0 1 0 0 1 0 H L L L 4: 0 1 0 0 1 0 H L L L 5: 0 1 0 0 1 0 H L L L 6: 0 1 0 0 1 0 H L L L 7: 0 1 0 0 1 0 H L L L 8: 0 1 0 0 1 0 H L L L 9: 0 1 0 0 1 0 H L L L 10: 0 1 0 0 1 0 H L L L 11: 0 1 0 0 1 0 H L L L 12: 0 1 0 0 1 0 H L L L 13: 0 1 0 0 1 0 H L L L 14: 0 1 0 0 1 0 H L L L Listing 5-3.
Vhd, the 8x4 memory block illustrates a more generic method of constructing memory of any word depth. ALU Datapth Implementation pepe, 5/23/96 entity mem8x4 is port( clk: in bit; mdatain: in one_mem_data; mdataout: out one_mem_data; address: in bit_vector (adw downto 0); nw: in bit); end mem8x4; architecture mem8x4_arch of mem8x4 is signal mword: mem_data; signal madd: bit_vector (adw downto 0); begin -- clocked memory! ALU Datapth Implementation pepe, 5/23/96 end if; else if nw='0' then word1 <= mdatain; else mdataout <= word1; end if; end if; end if; end process; end mem2x4_arch; Listing 6-2.
Vhd and therefore are available for use. Only the module ripp_adder4 is used structurally inside of the addtest module. Remaining modules such as full_adder and half adder are not shown inside of the addtest module; nevertheless, they were important in building the ripple carry adder ripp_adder4. The test wave form which illustrates the adder’s functionality is shown in Figure 5-3. In Figure 5-3, ain is set to “1111” and bin is set to “0011”. The output aout becomes “0010” with the overflow flag set to 1.